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RM0008
Advanced-control timers (TIM1&TIM8)
Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
Table 72.
TIMx Internal trigger connection (1)
Slave TIM
TIM1
TIM8
ITR0 (TS = 000)
TIM5
TIM1
ITR1 (TS = 001)
TIM2
TIM2
ITR2 (TS = 010)
TIM3
TIM4
ITR3 (TS = 011)
TIM4
TIM5
1. When a timer is not present in the product, the corresponding trigger ITRx is not available.
13.4.4
TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000
15
Res.
Res.
14
TDE
rw
13
COMD
E
rw
12
CC4D
E
rw
11
CC3D
E
rw
10
CC2D
E
rw
9
CC1D
E
rw
8
UDE
rw
7
BIE
rw
6
TIE
rw
5
COMI
E
rw
4
CC4IE
rw
3
CC3IE
rw
2
CC2IE
rw
1
CC1IE
rw
0
UIE
rw
Bit 15 Reserved, always read as 0.
Bit 14 TDE : Trigger DMA request enable
0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
Bit 13 COMDE : COM DMA request enable
0: COM DMA request disabled.
1: COM DMA request enabled.
Doc ID 13902 Rev 9
299/995
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